;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (c) 2001-2002 TIMEX Corporation.
; 
; This document is the property of, and contains information proprietary to
; TIMEX Corporation.  It is to be returned upon request.  Reproduction by any
; means, disclosure, or use of its contents for other than the expressed
; purpose for which it is loaned, without the written consent of TIMEX
; Corporation, is strictly prohibited.
;
; File Name:    HwMain.h
;
; Module Names: None
;                   
; Purpose:      Definitions for the HW module
;
; File Change History:
;
;               03/12/2002 RVD - Created HwMain.h
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;******************************************************************************
; INTERRUPT CONTROL PIN REDEFINITIONS
; The following list redefines the main interrupt priority  pins in terms of their 
; functionality.
;******************************************************************************
bI0I1                       EQU     (bI0Flag|bI1Flag)   ; used in the EI and DI macros
                                                        ; Consists of I0, I1 as a pair for enable/disable
                                                        ; ALL interropts


IntPriorityReg0             EQU     IntPriorityK00      ; K00-K07,SPI,STP and CLK interrupts 
                                                        ; priority Register
IntPriorityReg1             EQU     IntPriorityK10      ; K10-K11 and PT interrupts priority 
                                                        ; Register
;******************************************************************************
; CLOCK PIN REDEFINITIONS
; The following list redefines the main timer hardware pins in terms of their 
; functionality.
;******************************************************************************

; Main Timer Interrupt Enable Pins
b1HZENABLE                  EQU     bETM1               ; 1Hz interrupt enable bit 
                                                        ; (1 = enable)
b2HZENABLE                  EQU     bETM2               ; 2Hz interrupt enable bit 
b8HZENABLE                  EQU     bETM8               ; 8Hz interrupt enable bit
b32HZENABLE                 EQU     bETM32              ; 32Hz interrupt enable bit

; Main Timer Counter Pins
b1HZFLAG                    EQU     bFTM1               ; 1Hz interrupt factor bit 
                                                        ; (1 = caused interrupt)  
b2HZFLAG                    EQU     bFTM2               ; 2Hz interrupt factor bit 
b8HZFLAG                    EQU     bFTM8               ; 8Hz interrupt factor bit
b32HZFLAG                   EQU     bFTM32              ; 32Hz interrupt factor bit

; Macro Parameter definitions
INT1HZ                      EQU     bETM1               ; 1Hz interrupt enable Mask
INT2HZ                      EQU     bETM2               ; 2Hz interrupt enable Mask
INT8HZ                      EQU     bETM8               ; 8Hz interrupt enable Mask
INT32HZ                     EQU     bETM32              ; 32Hz interrupt enable Mask

;******************************************************************************
; STOPWATCH PIN REDEFINITIONS
; The following list redefines the main stopwatch hardware pins in terms of their 
; functionality.
;******************************************************************************

; Main Stopwatch Interrupt Enable Pins
b1HZSTPENABLE               EQU     bESW1               ; 1Hz interrupt enable bit (1 = enable)
b10HZSTPENABLE              EQU     bESW10              ; 10Hz interrupt enable bit 
b100HZSTPENABLE             EQU     bESW100             ; 100Hz interrupt enable bit

STPINT1HZ                   EQU     bESW1
STPINT10HZ                  EQU     bESW10
STPINT100HZ                 EQU     bESW100

; Main Stopwatch Counter Pins
b1HZSTPFLAG                 EQU     bFSW1               ; 1Hz interrupt factor bit 
                                                        ; (1 = caused interrupt)  
b10HZSTPFLAG                EQU     bFSW10              ; 2Hz interrupt factor bit 
b100HZSTPFLAG               EQU     bFSW100             ; 8Hz interrupt factor bit

; Macro Parameter definitions
INT1HZSTP                   EQU     bESW1               ; 1Hz interrupt enable Mask
INT10HZSTP                  EQU     bESW10              ; 2Hz interrupt enable Mask
INT100HZSTP                 EQU     bESW100             ; 8Hz interrupt enable Mask

;******************************************************************************
; Buzzer DUTY Cycle definitions
;   Acts as a psedo volume control
;******************************************************************************
DUTY_0                      EQU     (bDUTY2|bDUTY1|bDUTY0)
DUTY_1                      EQU     (bDUTY2|bDUTY1)
DUTY_2                      EQU     (bDUTY2|bDUTY0)
DUTY_3                      EQU     bDUTY2
DUTY_4                      EQU     (bDUTY1|bDUTY0)
DUTY_5                      EQU     bDUTY1
DUTY_6                      EQU     bDUTY0
DUTY_7                      EQU     0

;******************************************************************************
; Buzzer FREQUENCY definitions
;******************************************************************************

FREQ_4096                   EQU     0
FREQ_3276                   EQU     bBZFQ0
FREQ_2730                   EQU     bBZFQ1
FREQ_2340                   EQU     (bBZFQ1|bBZFQ0)
FREQ_2048                   EQU     bBZFQ2
FREQ_1638                   EQU     (bBZFQ2|bBZFQ0)
FREQ_1365                   EQU     (bBZFQ2|bBZFQ1)
FREQ_1170                   EQU     (bBZFQ2|bBZFQ1|bBZFQ0)


;******************************************************************************
; PROGRAMMABLE TIMER PIN REDEFINITIONS
; The following list redefines the hardware pins in terms of their 
; functionality.
;******************************************************************************
PTMODE_8                    EQU     00000000B           ; 8 bit mode 2 channel = clear mode bit 

PTMODE_16                   EQU     bMODE16             ; 16 bit mode 1 channel = set mode bit

PTCKSEL0_OSC1               EQU     00000000B           ; Prescaler 0 source clock selection 
                                                        ; for timer 0
PTCKSEL0_OSC3               EQU     bCKSEL0

PTCKSEL1_OSC1               EQU     00000000B           ; Prescaler 1 source clock selection 
                                                        ; for timer 1
PTCKSEL1_OSC3               EQU     bCKSEL1
    
PTCHSEL_TIMER0              EQU     00000000B           ; TOUT output channel selection 
                                                        ; Timer0/Timer1
PTCHSEL_TIMER1              EQU     bCHSEL  

PTPTOUT_OFF                 EQU     00000000B           ; TOUT frequency output control

PTPTOUT_ON                  EQU     bPTOUT

; Timer 0
EVCNTMODE_ON                EQU     bEVCNT              ; Event counter mode on
EVCNTMODE_OFF               EQU     00000000B           ; Timer mode on

CONTMODE_ON                 EQU     bCONT0              ; continious mode
CONTMODE_OFF                EQU     00000000B           ; one shot mode

DIVRATIO_1                  EQU     00000000B           ; Clock source/1 dividing ratio
DIVRATIO_4                  EQU     bPSC00              ; Clock source/4 dividing ratio
DIVRATIO_16                 EQU     bPSC01              ; Clock source/16 dividing ratio
DIVRATIO_64                 EQU     bPSC00|bPSC01       ; Clock source/64 dividing ratio

NDIVRATIO_1                 EQU     1H                  ; Clock source/1 dividing ratio
NDIVRATIO_4                 EQU     4H                  ; Clock source/4 dividing ratio
NDIVRATIO_16                EQU     10H                 ; Clock source/16 dividing ratio
NDIVRATIO_64                EQU     40H                 ; Clock source/64 dividing ratio

PULSEPOL_ON                 EQU     bPLPOL              ; Pulse polarity select. 
PULSEPOL_OFF                EQU     00000000B           ;  1 = Rising edge trigger
                                                        ;  0 = falling edge trigger

FUNCTIONSEL_ON              EQU     bFCSEL              ; Pulse width measurement function select
FUNCTIONSEL_OFF             EQU     00000000B           ;  1 = On, 0 = Off

HWTIMER0INT                 EQU     bEPT0               ; Timer 0 interrupt enable pin
HWTIMER1INT                 EQU     bEPT1               ; Timer 1 interrupt enable pin
    
HWTIMER0FACTOR              EQU     bFPT0               ; Timer 0 interrupt factor flag
HWTIMER1FACTOR              EQU     bFPT1               ; Timer 1 interrupt factor flag

; Programmable Timer reload times
; The timers in this project are used as follows:
;
; TIMER0 is used to generate the time base for the LCD Scrolling. The scrolling function 
; will shift the display 1 pixel column to the left when the Timer0 count expires.
;
; The scrolling frequency is dependant on:
;   The reload time chosen for the Timer0 reload register
;   Which Clock (OSC1 or OSC3) is selected as the time base for the Timer.
;   The pre-scaler value chosen. 
;
; For consistency, OSC1 will ALAWAYS be selected as the time base.
;
; Given a certain desired Scroll Frequency (SCROLL_FREQ_xxHZ), the reload time is 
; calculated as follows:
;
;   TMR0_SCROLL_RELOAD = OSC1FREQ/DIVRATIO_XX/SCROLL_FREQ_xxHZ

; Typical Scrolling Frequencies
SCROLL_FREQ_8HZ             EQU     8
SCROLL_FREQ_10HZ            EQU     10
SCROLL_FREQ_12HZ            EQU     12
SCROLL_FREQ_14HZ            EQU     14
SCROLL_FREQ_16HZ            EQU     16

; Default Scroll Frequency - stored in ICB
HW_DEFAULT_SCROLL_FREQ      EQU     SCROLL_FREQ_12HZ

; Default Scroll Reload value
HW_TMR0_DEFAULT_SCROLL_RELOAD  EQU     OSC1FREQ/NDIVRATIO_64/HW_DEFAULT_SCROLL_FREQ

; Value for pre-scrolling 1 second time out
HW_TMR0_PRE_SCROLLING_COUNT EQU     HW_TMR0_DEFAULT_SCROLL_RELOAD

;**************************************************************************************************
;   Clock Frequencies
;**************************************************************************************************
; OSC3 External Crystal Frequencies 
; These are all capable of producing 2400/4800/9600 baud rates
HWOSC3FREQUENCY4_9152MHz    EQU     4915200
HWOSC3FREQUENCY3_072MHz     EQU     3072000
HWOSC3FREQUENCY2_4576MHz    EQU     2457600
HWOSC3FREQUENCY1_8432MHz    EQU     1843200
HWOSC3FREQUENCY1_2288MHz    EQU     1228800
HWOSC3FREQUENCY614_4KHz     EQU      614400
; OSC1 External Crystal Frequency   
HWOSC1FREQUENCY32_768KHz    EQU     32768

; Frequencies used in this development
OSC3FREQ                    EQU     HWOSC3FREQUENCY2_4576MHz
OSC1FREQ                    EQU     HWOSC1FREQUENCY32_768KHz

;**************************************************************************************************
;   SVD Battery test definitions
;**************************************************************************************************
; Mask for retrieving stored battery test level (upper nibble of shared variable)
HW_MASK_BATTERY_LEVEL       EQU     11110000b
; Battery test levell which indicates we should bypass the battery level test (highest level)
HW_SVD_BYPASS_TEST          EQU     HW_SVD_LEVEL_4p17_VOLTS
; Default level used in POR reset for programming an un-programmed ICB.
HW_SVD_BATTERY_DEFAULT      EQU     HW_SVD_BYPASS_TEST

; Battery Test Levels.
; These are the averages, all values are +/-8%
HW_SVD_LEVEL_1p83_VOLTS     EQU                        bSVD0
HW_SVD_LEVEL_2p00_VOLTS     EQU                  bSVD1
HW_SVD_LEVEL_2p17_VOLTS     EQU                 (bSVD1|bSVD0)
HW_SVD_LEVEL_2p33_VOLTS     EQU            bSVD2
HW_SVD_LEVEL_2p50_VOLTS     EQU           (bSVD2|      bSVD0)
HW_SVD_LEVEL_2p67_VOLTS     EQU           (bSVD2|bSVD1      )
HW_SVD_LEVEL_2p83_VOLTS     EQU           (bSVD2|bSVD1|bSVD0)
HW_SVD_LEVEL_3p00_VOLTS     EQU      bSVD3
HW_SVD_LEVEL_3p17_VOLTS     EQU     (bSVD3|            bSVD0)
HW_SVD_LEVEL_3p33_VOLTS     EQU     (bSVD3|      bSVD1      )
HW_SVD_LEVEL_3p50_VOLTS     EQU     (bSVD3|      bSVD1|bSVD0)
HW_SVD_LEVEL_3p67_VOLTS     EQU     (bSVD3|bSVD2            )
HW_SVD_LEVEL_3p83_VOLTS     EQU     (bSVD3|bSVD2|      bSVD0)
HW_SVD_LEVEL_4p00_VOLTS     EQU     (bSVD3|bSVD2|bSVD1      )
HW_SVD_LEVEL_4p17_VOLTS     EQU     (bSVD3|bSVD2|bSVD1|bSVD0)
;**************************************************************************************************
;   BOND Definition
;**************************************************************************************************
HWBondPort                  EQU     InOutPortP00
HWBondPortControl           EQU     P00Control


;**************************************************************************************************
;   Delay loop definitions
;**************************************************************************************************
; The loop execution requires 6 instruction cycles (12 clock ticks)
; So the individual execution time for each cycle is 12/OSC.
; At OSC1, this is 12/32768 = 360uS. 
; Thus, to achieve a delay of 5mSec, we calculate: 5mSec/360uS = 13.8888 =~ 14
; Maximum time delay at OSC1 is 256*12/32768 = 93mSec. To achieve this, load
; 0 as the initial delay value.    
HW_01_MSEC                  EQU      3      ; Delay loop counter for 1 mSec delay
HW_05_MSEC                  EQU     14      ; Delay loop counter for 5 mSec delay
HW_10_MSEC                  EQU     28      ; Delay loop counter for 10 mSec delay
HW_15_MSEC                  EQU     42      ; Delay loop counter for 15 mSec delay
HW_20_MSEC                  EQU     56      ; Delay loop counter for 20 mSec delay
